The present invention is directed to a method and apparatus for increasing the flexibility of an address counter which is used to generate addresses for accessing an array of storage cells.
Random access memory chips, and in particular dynamic random access memory chips (DRAMs) contain high density storage cells. In the testing of such memory devices, individual cells are tested to locate failing elements and repair them. To address these cells, the tester must generate row and column addresses which are associated with them.
In many automated test processes, internal address counters are used instead of a tester counter to generate test addresses for the rows and columns. In this setting, a logical unit integrated in the DRAM chip generates these addresses internally according to a predetermined pattern.
This scheme is very advantageous from a test time and cost point of view, but it often limits the flexibility of the tester to address DRAM cells. In accordance with normal test procedure, an internal counter is reset at the beginning of the procedure. The counter is incremented in the event of a command to access the next row or column. Each address of the counter is incremented in the event of an overflow of the less significant bits and the command signal being high. Due to the limited communication between the tester and the internal address counter, the test engineer has to implement a workaround to jump to certain array location(s) and perform special test features. One of these workarounds is using dummy commands to increment the counter and then execute the actual command once the address is reached. These workarounds in the nature of dummy commands may cost test time and add to the complexity of the test procedure.